| Clock managementThe clock controller distributes the clocks coming from different oscillators to the core andthe peripherals. It also manages clock gating for low power modes and ensures clockrobustness. It features:●Clock prescaler: to get the best tradeoff between speed and current consumption, theclock frequency to the CPU and peripherals can be adjusted by a programmableprescaler●Safe clock switching: clock sources can be changed safely on the fly in run modethrough a configuration register.●Clock management: to reduce power consumption, the clock controller can stop theclock to the core, individual peripherals or memory.●Master clock source: three different clock sources can be used to drive the masterclock:–1-24 MHz high-speed external crystal (HSE), that can supply a PLL–16 MHz high-speed internal RC oscillator (HSI), trimmable by software, that cansupply a PLL–Multispeed internal RC oscillator (MSI), trimmable by software, able to generate 7frequencies (65.5 kHz, 131 kHz, 262 kHz, 524 kHz, 1.05 MHz, 2.1 MHz, 4.2 MHz)with a consumption proportional to speed, down to 750 nA typical. When a32.768 kHz clock source is available in the system (LSE), the MSI frequency canbe trimmed by software down to a ±0.5% accuracy |
 |
|
|
手机站
您当前位置是：产品大全 >> 电子元器件 >>
集成电路(IC)
免责声明：以上所展示的信息由会员自行提供，内容的真实性、准确性和合法性由发布会员负责，www.qy6.com对此不承担任何责任。如有侵犯您的权益，请来信通知删除。
联系信息
